View TSSOP16_6149756.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the pcal9554b and pcal9554c are a low-voltage 8-bit general purpose input/output (gpio) expanders with interrupt and weak pull-up for i 2 c-bus/smbus applications. the only difference between the pcal9554b and pcal9554c is their i 2 c-bus fixed address, allowing a larger number of the same device on the i 2 c-bus with no chance of address conflicts. nxp i/o expanders provide a simple solution when additional i/os are needed while keeping intercon nections to a minimum, for exam ple, in acpi power switches, sensors, push buttons, leds, fan control, etc. in addition to providing a flexible set of gpios, the wide v dd range of 1.65 v to 5.5 v allows the pcal9554b/pcal9554c to interface with next-generation microprocessors and microcontrollers where supply levels are dropping down to conserve power. the pcal9554b/pcal9554c contains the pc a9554a register set of four 8-bit configuration, input, output, and polarity inversion registers, and additionally, the pcal9554b/pcal9554c has ag ile i/o, which are additiona l features specifically designed to enhance the i/o. these additional features are: programmable output drive strength, latchable inputs, programmable pull-up /pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs. the pcal9554b is a pin-for-pin replacement for the pca9554, while the pcal9554c replaces the pca9554a, however both versions power-up with all i/o interrupted masked. this mask default allows for a board bring-up free of spurious interrupts at power-up. the pcal9554b/pcal9554c open-drain interrupt (int ) output is activated when any input state differs from its corresponding input po rt register state and is used to indicate to the system master that an input state has changed. int can be connected to the interrupt input of a microcontroller. by sending an interrupt signal on this line, the remote i/o can inform the microcontroller if there is incoming data on its ports without having to communicate via the i 2 c-bus. thus, the pcal9554b or pcal9554c can remain a simple slave device. the device outputs have 25 ma sink capabilitie s for directly driving leds while consuming low device current. three hardware pins (a0, a1, a2) select the fixed i 2 c-bus address and allow up to eight devices to share the same i 2 c-bus/smbus. the pcal9554b and pcal9554c differ only in their base i 2 c-bus addresses permitting a total of 16 of the same devices on the i 2 c-bus, minimizing the chance of address conflict, even in the most complex system. pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus and smbus low power i/o port with interrupt, weak pul l-up and agile i/o rev. 2 ? 10 december 2012 product data sheet
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 2 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 2. features and benefits ? i 2 c-bus to parallel port expander ? operating power supply voltage range of 1.65 v to 5.5 v ? low standby current consumption: ? 1.5 ? a (typical at 5 v v dd ) ? 1.0 ? a (typical at 3.3 v v dd ) ? schmitt-trigger action allows slow input tran sition and better switching noise immunity at the scl and sda inputs ? v hys =0.10 ? v dd (typical) ? 5 v tolerant i/os ? open-drain active low interrupt output (int ) ? 400 khz fast-mode i 2 c-bus ? internal power-on reset ? power-up with all channels configured as inputs ? no glitch on power-up ? latched outputs with 25 ma drive maximu m capability for directly driving leds ? latch-up performance exceeds 100 ma per jesd78, class ii ? esd protection exceeds jesd22 ? 2000 v human body model (a114-a) ? 1000 v charged-device model (c101) ? packages offered: TSSOP16 and hvqfn16 2.1 agile i/o features ? pin to pin replacement for pca9554 and pca9554b, pca9554a and pca9554c with interrupts disabled at power-up ? software backward compatible with pca9554 and pca9554b, pca9554a and pca9554c ? output port configuration: bank selectable push-pull or open-drain output stages ? interrupt status: read-only register identifies the source of an interrupt ? bit-wise i/o programming features: ? output drive strength: four programmable drive strengths to reduce rise and fall times in low capacitance applications ? input latch: input port register values changes are kept until the input port register is read ? pull-up/pull-down enable: floating input or pull-up/down resistor enable ? pull-up/pull-down selection: 100 k ? pull-up/down resistor selection ? interrupt mask: mask prevents the generation of the interrupt when input changes state
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 3 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 3. ordering information 3.1 ordering options 4. block diagram table 1. ordering information type number topside mark package name description version pcal9554bbs l4b hvqfn16 plastic thermal enh anced very thin quad flat package; no leads; 16 terminals; body 3 ? 3 ? 0.85 mm sot758-1 pcal9554bpw pl9554b TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 pcal9554cbs l4c hvqfn16 plastic thermal enh anced very thin quad flat package; no leads; 16 terminals; body 3 ? 3 ? 0.85 mm sot758-1 pcal9554cpw pl9554c TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 table 2. ordering options type number orderable part number package packing method minimum order quantity temperature range pcal9554bbs pcal9554bbshp hvq fn16 reel pack, smd, 13-inch, turned 6000 t amb = ? 40 ? c to +85 ?c pcal9554bpw pcal9554bpwj t ssop16 reel pack, smd, 13-inch 2500 t amb = ? 40 ? c to +85 ?c pcal9554cbs pcal9554cbshp hvqfn16 reel pack, smd, 13-inch, turned 6000 t amb = ? 40 ? c to +85 ?c pcal9554cpw pcal9554cpwj t ssop16 reel pack, smd, 13-inch 2500 t amb = ? 40 ? c to +85 ?c remark: all i/os are set to inputs at reset. fig 1. block diagram of pcal9554b/pcal9554c pcal9554b pcal9554c power-on reset 002aah204 input filter scl sda v dd p0 v ss 8-bit write pulse read pulse p2 p1 p3 lp filter v dd int a0 a1 p4 p6 p5 p7 i 2 c-bus/smbus control input/ output ports a2
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 4 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 5. pinning information 5.1 pinning 5.2 pin description [1] all i/o are configured as input at power-on. [2] hvqfn16 package die supply ground is connected to both the v ss pin and the exposed center pad. the v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. fig 2. pin configuration for TSSOP16 fig 3. pin configuration for hvqfn16 v dd sda scl int p7 p6 p5 p4 a0 a1 a2 p0 p1 p2 p3 v ss pcal9554bpw pcal9554cpw 002aah205 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 002aah206 transparent top view p2 p6 p1 p7 p0 int scl p3 v ss p4 p5 a1 a0 v dd sd a 4 9 3 10 2 11 1 12 5 6 7 8 16 15 14 13 terminal 1 index area a2 pcal9554bbs pcal9554cbs table 3. pin description symbol pin description TSSOP16 hvqfn16 a0 1 15 address input 0 a1 2 16 address input 1 a2 3 1 address input 2 p0 [1] 4 2 port p input/output 0 p1 [1] 5 3 port p input/output 1 p2 [1] 6 4 port p input/output 2 p3 [1] 7 5 port p input/output 3 v ss 86 [2] supply ground p4 [1] 9 7 port p input/output 4 p5 [1] 10 8 port p input/output 5 p6 [1] 11 9 port p input/output 6 p7 [1] 12 10 port p input/output 7 int 13 11 interrupt output (open-drain) scl 14 12 serial clock line sda 15 13 serial data line v dd 16 14 supply voltage
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 5 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 6. functional description refer to figure 1 ? block diagram of pcal9554b/pcal9554c ? . 6.1 device address a2, a1 and a0 are the hardware address package pins and are held to either high (logic 1) or low (logic 0) to assign one of the eight possible slave addresses. the last bit of the slave address (r/w ) defines the operation (read or write) to be performed. a high (logic 1) selects a read operation, while a low (logic 0) selects a write operation. 6.2 pointer register and command byte following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the poin ter register in the pcal9554b/pcal9554c. two bits of this data byte state the operation (read or write) and the internal registers (input, output, polarity inversi on, or configuration) that will be affected. bit 6 in conjunction with the lower three bits of the command byte are used to point to the extended features of the device (agile i/o). this register is write only. a. pcal9554b address b. pcal9554c address fig 4. device address r/w 002aah207 0 1 0 0 a2 a1 a0 slave address fixed hardware selectable r/w 002aah208 0 1 1 1 a2 a1 a0 slave address fixed hardware selectable fig 5. pointer register bits 002aaf540 b7 b6 b5 b4 b3 b2 b1 b0
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 6 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port [1] undefined. 6.3 interface definition 6.4 register descriptions 6.4.1 input port register (00h) the input port register (register 0) reflects th e incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the configuration register. the input port register is read only; writes to this register have no effect. the default value ?x? is determined by the externally applied logic level. an input port register read operation is performed as described in section 7.2 ? read commands ? . 6.4.2 output port register (01h) the output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the configuration register. bit values in these registers have no effect on pins defined as inputs. in turn, reads from this regi ster reflect the value th at was written to this register, not the actual pin value. table 4. command byte pointer register bits command byte (hexadecimal) register protocol power-up default b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 00h input port read byte xxxx xxxx [1] 0 0 0 0 0 0 0 1 01h output port read/write byte 1111 1111 0 0 0 0 0 0 1 0 02h polarity inversion read/write byte 0000 0000 0 0 0 0 0 0 1 1 03h configuration read/write byte 1111 1111 0 1 0 0 0 0 0 0 40h output drive strength 0 read/write byte 1111 1111 0 1 0 0 0 0 0 1 41h output drive strength 1 read/write byte 1111 1111 0 1 0 0 0 0 1 0 42h input latch read/write byte 0000 0000 0 1 0 0 0 0 1 1 43h pull-up/pull-down enable read/write byte 0000 0000 0 1 0 0 0 1 0 0 44h pull-up/pull-down selection read/write byte 1111 1111 0 1 0 0 0 1 0 1 45h interrupt mask read/write byte 1111 1111 0 1 0 0 0 1 1 0 46h interrupt status read byte 0000 0000 0 1 0 0 0 1 1 1 47h output port configuration read/write byte 0000 0000 table 5. interface definition byte bit 7 (msb) 6 5 4 3 2 1 0 (lsb) i 2 c-bus slave address l h l/h l/h a2 a1 a0 r/w i/o data bus p7 p6 p5 p4 p3 p2 p1 p0 table 6. input port register (address 00h) bit 7 6 5 4 3 2 1 0 symbol i7 i6 i5 i4 i3 i2 i1 i0 default xxxxxxxx
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 7 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 6.4.3 polarity inversion register (02h) the polarity inversion register (register 2) a llows polarity inversion of pins defined as inputs by the configuration register. if a bit in this register is set (written with ?1?), the corresponding port pin?s polarity is inverted. if a bi t in this register is cleared (written with a ?0?), the corresponding port pin?s original polarity is retained. 6.4.4 configuration register (03h) the configuration register (register 3) configures the direction of the i/o pins. if a bit in this register is set to 1, the corresponding port pin is enabled as a high-impedance input. if a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. 6.4.5 output drive strength registers (40h, 41h) the output drive strength registers control th e output drive level of the gpio. each gpio can be configured independently to a certain output current level by two register control bits. for example, port 7 is controlled by register 41 cc7 (bits [7:6]), port 6 is controlled by register 41 cc6 (bits [5:4]). the output drive level of the gpio is programmed 00b = 0.25 ? , 01b = 0.5 ? , 10b = 0.75 ? or 11b = 1 ? of the drive capability of the i/o. see section 8.2 ? output drive strength control ? for more details. table 7. output port register (address 01h) bit 7 6 5 4 3 2 1 0 symbol o7 o6 o5 o4 o3 o2 o1 o0 default 11111111 table 8. polarity inversion register (address 02h) bit 7 6 5 4 3 2 1 0 symbol n7 n6 n5 n4 n3 n2 n1 n0 default 00000000 table 9. configuration register (address 03h) bit 7 6 5 4 3 2 1 0 symbol c7 c6 c5 c4 c3 c2 c1 c0 default 11111111 table 10. current control register (address 40h) bit 7 6 5 4 3 2 1 0 symbol cc3 cc2 cc1 cc0 default 11111111 table 11. current control register (address 41h) bit 7 6 5 4 3 2 1 0 symbol cc7 cc6 cc5 cc4 default 11111111
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 8 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 6.4.6 input latch register (42h) the input latch register enables and disabl es the input latch of the i/o pins. these registers are effective only when the pin is configured as an input port. when an input latch register bit is 0, the corresponding inpu t pin state is not latched. a state change in the corresponding input pin generates an interrup t. a read of the input port register clears the interrupt. if the input goes back to its initial logic state be fore the input port register is read, then the interrupt is cleared. when an input latch register bit is 1, the corresponding input pin state is latched. a change of state of the input generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register (registers 0). a read of the input port register clears the interrupt. if the in put pin returns to its initial logic state before the input port register is read, then the interr upt is not cleared and the corres ponding bit of the input port register keeps the logic value that initiated the interrupt. see figure 11 . for example, if the p4 input was as logic 0 and the input goes to logic 1 then back to logic 0, the input port register will capture this chang e and an interrupt is generated (if unm asked). when the read is performed on the input port register, the interrupt is cleared, assuming there were no additional input(s) that have changed, and bit 4 of the in put port register will read ?1?. the next read of the input port register bit 4 should now read ?0?. an interrupt remains active when a non-latc hed input simultaneously switches state with a latched input and then returns to its original state. a read of the input port register reflects only the change of state of the latched input and also clears the interrupt. the interrupt is not cleared if the input latch register change s from latched to non-latched configuration. if the input pin is changed from latched to non-latched input, a read from the input port register reflects the current port logic level. if the input pin is changed from non-latched to latched input, the read from the input port register reflects the latched logic level. 6.4.7 pull-up/pull-down enable register (43h) this register allows the user to enable or disable pull-up/pull-down resistors on the i/o pins. setting the bit to logic 1 enables the sele ction of pull-up/pull-down resistors. setting the bit to logic 0 disconnects the pull-up/pull-down resistors from the i/o pins. also, the resistors will be disconnected when the outputs are configur ed as open-drain outputs (see section 6.4.11 ). use the pull-up/pull-down registers to select either a pull-up or pull-down resistor. the default value enables pull-up resistors on all i/o pins to match with the non-agile i/o devices pca9554b and pca9554c. table 12. input latch register (address 42h) bit 7 6 5 4 3 2 1 0 symbol l7 l6 l5 l4 l3 l2 l1 l0 default 00000000 table 13. pull-up/pull-down enable register (address 43h) bit 7 6 5 4 3 2 1 0 symbol pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 default 11111111
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 9 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 6.4.8 pull-up/pull-down selection register (44h) the i/o port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down selection register. setting a bit to logic 1 selects a 100 k ? pull-up resistor for that i/o pin. setting a bit to logic 0 selects a 100 k ? pull-down resistor for that i/o pin. if the pull-up/down feature is disconnec ted, writing to this register will have no effect on i/o pin. typical value is 100 k ? with minimum of 50 k ? and maximum of 150 k ? . 6.4.9 interrupt mask register (45h) interrupt mask register is set to logic 1 upon power-on, disabling interrupts during system start-up. interrupts may be enabled by setting corresponding mask bits to logic 0. if an input changes state and the corresponding bit in the interrupt mask register is set to 1, the interrupt is masked and the interrupt pin (int ) will not be asserted. if the corresponding bit in the interrupt mask register is set to 0, the interrupt pin will be asserted. when an input changes state and the resulting interrupt is masked (interrupt mask bit is 1), setting the input mask regist er bit to 0 will cause the interr upt pin to be asserted. if the interrupt mask bit of an input that is currently the source of an interrupt is set to 1, the interrupt pin will be de-asserted. 6.4.10 interrupt status register (46h) this read-only register is used to identify the source of an interrupt. when read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. a logic 0 indicates that the input pin is not the source of an interrupt. when a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return logic 0. table 14. pull-up/pull-down selection register (address 44h) bit 7 6 5 4 3 2 1 0 symbol pud7 pud6 pud5 pud4 pud3 pud2 pud1 pud0 default 11111111 table 15. interrupt mask register (address 45h) bit 7 6 5 4 3 2 1 0 symbol m7 m6 m5 m4 m3 m2 m1 m0 default 11111111 table 16. interrupt status register (address 46h) bit 7 6 5 4 3 2 1 0 symbol s7 s6 s5 s4 s3 s2 s1 s0 default 00000000
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 10 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 6.4.11 output port configuration register (47h) the output port configuration register select s port-wise push-pull or open-drain i/o stage. a logic 0 configures the i/o as push-pull (q1 and q2 are active, see figure 6 ). a logic 1 configures the i/o as open-drain (q1 is disabled, q2 is active). 6.5 i/o port when an i/o is configured as an input, fets q1 and q2 are off, which creates a high-impedance input. the input voltage may be raised above v dd to a maximum of 5.5 v. if the i/o is configured as an output, q1 or q2 is enabled, depending on the state of the output port register. in this case, there are low-impedance paths between the i/o pin and either v dd or v ss . the external voltage applied to th is i/o pin should not exceed the recommended levels for proper operation. table 17. output port configuration register (address 47h) bit 7 6 5 4 3 2 1 0 symbol reserved oden0 default 00000000 on power-up or reset, all registers return to default values. fig 6. simplified schematic of the i/os (p0 to p7) interrupt mask v dd p0 to p7 output port register data configuration register dq ck q data from shift register write configuration pulse output port register dq ck write pulse polarity inversion register dq ck data from shift register write polarity pulse input port register dq ck read pulse input port register data 002aah101 ff data from shift register ff ff ff q1 q2 v ss to int pull-up/pull-down control esd protection diode 100 k v dd esd protection diode input port latch dq en latch read pulse input latch register dq ck ff data from shift register write input latch pulse
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 11 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 6.6 power-on reset when power (from 0 v) is applied to v dd , an internal power-on reset holds the pcal9554b/pcal9554c in a reset condition until v dd has reached v por . at that time, the reset condition is released and the pcal9554b/pcal9554c registers and i 2 c-bus/smbus state machine initialize to their default states. after that, v dd must be lowered to below v por and back up to the operating volt age for a power-reset cycle. see section 8.4 ? power-on reset requirements ? . 6.7 interrupt output (int ) an interrupt is generated by an y rising or falling edge of t he port inputs in the input mode. after time t v(int) , the signal int is valid. resetting the interrupt circuit is achieved when data on the port is changed to the original setting or when data is read from the port that generated the interrupt (see figure 10 ). resetting occurs in the read mode at the acknowledge (ack) or not acknowledge (nack) bit after the rising edge of the scl signal. interrupts that occur during the ack or nack clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. each change of the i/os after resetting is detected and is transmitted as int . a pin configured as an output cannot cause an interrupt. changing an i/o from an output to an input may cause a false interrupt to occu r, if the state of the pin does not match the contents of the input port register. the int output has an open-drain structure and requires a pull-up resistor to v dd . int should be connected to the voltage source of the device that requires the interrupt information. when using the input latch feature, the input pin state is latched. the interrupt is reset only when data is read from the port that generated the interrupt. the reset occurs in the read mode at the acknowledge (ack) or not acknowledge (nack) bit after the rising edge of the scl signal.
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 12 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 7. bus transactions the pcal9554b/pcal9554c is an i 2 c-bus slave device. data is exchanged between the master and pcal9554b/pcal9554c through write and read commands using i 2 c-bus. the two communication lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive su pply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.1 write commands data is transmitted to the pcal9554b/pcal9554c by sending the device address and setting the least significant bi t (lsb) to a logic 0 (see figure 4 for device address). the command byte is sent after the address and de termines which register receives the data that follows the command byte. there is no limitation on the number of data bytes sent in one write transmission. (1) pcal9554b address shown. address for pcal9554c is 0111,a2,a1,a0. fig 7. write to output port register 0 a s slave address (1) start condition r/w acknowledge from slave 002aah124 0000001 0 command byte a acknowledge from slave 12345678 scl 9 sda data 1 a write to port data out from port t v(q) acknowledge from slave data 1 valid data to port 1 0 0 a2 a1 a0 0 p stop condition (1) pcal9554b address shown. address for pcal9554c is 0111,a2,a1,a0. fig 8. write to configuration or polarity inversion registers 0 a s slave address (1) start condition r/w acknowledge from slave 002aah125 0 0 0 0 0 1/0 1/0 0 command byte a acknowledge from slave 12345678 scl 9 sda data 1 a acknowledge from slave data to register 1 0 0 a2 a1 a0 0 p stop condition
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 13 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 7.2 read commands to read data from the pcal9554b/pcal9554c, the bus master must first send the pcal9554b/pcal9554c address with the least significant bit set to a logic 0 (see figure 4 for device address). the command byte is sent after the address and determines which register is to be accessed. after a restart the device address is sent agai n, but this time the lsb is set to a logic 1. data from the register defined by th e command byte then is sent by the pcal9554b/pcal9554c (see figure 9 and figure 10 ). data is clocked into the register on the risi ng edge of the ack clock pulse. there is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data. (1) pcal9554b address shown. address for pcal9554c is 0111,a2,a1,a0. fig 9. read from register a s start condition r/w acknowledge from slave 002aah126 a acknowledge from slave sda a p acknowledge from master data (first byte) slave address (1) stop condition s (repeated) start condition (cont.) (cont.) 1 0 0 a2 a1 a0 1 a 0 r/w acknowledge from slave slave address (1) at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter na no acknowledge from master command byte 1 0 0 a2 a1 a0 0 0 data from register data (last byte) data from register transfer of data can be stopped at any time by a stop condition. when this occurs, data present at the latest acknowledge phase is valid (output mode). it is assumed that the command byte has previously been programmed with 00h (read input port register). this figure eliminates the command byte transfer, a restart, and slave address call between the in itial slave address call and actual data transfer from p port (see figure 9 ). (1) pcal9554b address shown. address for pcal9554c is 0111,a2,a1,a0. fig 10. read input port register (non-latched) 1 0 0 a2 a1 a0 1 a s0 slave address (1) start condition r/w acknowledge from slave 002aah127 data from port a acknowledge from master sda 1 no acknowledge from master read from port data into port data from port data 1 data 4 int data 4 data 2 data 3 p stop condition t v(int) t rst(int) t h(d) t su(d) 12345678 scl 9 data 1 data 5 int is cleared by read from port stop not needed to clear int
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 14 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port transfer of data can be stopped at any time by a stop condition. when this occurs, data present at the latest acknowledge phase is valid (output mode). it is assumed that the command byte has previously been programmed with 00h (read input port register). this figure eliminates the command byte transfer, a restart, and slave address call between the in itial slave address call and actual data transfer from p port (see figure 9 ). (1) pcal9554b address shown. address for pcal9554c is 0111,a2,a1,a0. fig 11. read input port register (latch enabled) 1 0 0 a2 a1 a0 1 a s0 slave address (1) start condition r/w acknowledge from slave 002aah209 data from port a acknowledge from master sda 1 no acknowledge from master read from port data into port data from port data 1 data 1 int data 2 data 2 p stop condition t v(int) t rst(int) t h(d) t su(d) 12345678 scl 9 data 1 int is cleared by read from port stop not needed to clear int
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 15 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 8. application design-in information 8.1 minimizing i dd when the i/os are used to control leds when the i/os are used to control leds, they are normally connected to v dd through a resistor as shown in figure 12 . since the led acts as a diode, when the led is off the i/o v i is about 1.2 v less than v dd . the supply current, i dd , increases as v i becomes lower than v dd . designs needing to minimize current consumpt ion, such as battery power applications, should consider maintaining the i/o pins greater than or equal to v dd when the led is off. figure 13 shows a high value resist or in parallel with the led, which is not needed with the pcal9554b or pcal9554c that integrate a weak pull-up resistor on all pins. figure 14 shows v dd less than the led supply voltage by at least 1.2 v. both of these methods maintain the i/o v i at or above v dd and prevents additional supply current consumption when the led is off. device address is 0100 000x for th is example using pcal9554b ( address for pcal9554c is 0111 000x). p0, p2, p3 configured as outputs. p1, p4, p5 configured as inputs. p6, p7 are not used and need 100 k ? pull-up resistors to protect them from fl oating or the internal pull-up or pull-down selected. (1) no resistors are required for inputs (on p port) that may float due to the weak pull-up integrated into the device. fig 12. typical application pcal9554b p0 p1 scl sda v dd (3.3 v) master controller scl sda int p2 v dd v dd v ss int 10 k sub-system 1 (e.g., temp sensor) p3 int sub-system 2 (e.g., counter) reset controlled switch (e.g., cbt device) a b enable v ss 002aah211 10 k 10 k 2 k 100 k ( 3) (1) p4 p5 a1 a0 sub-system 3 (e.g., alarm system) alarm v dd p6 p7 a2
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 16 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 8.2 output drive strength control the output drive strength registers allow the user to control the output drive level of the gpio. each gpio can be configured independe ntly to one of the four possible output current levels. by programming these bits the user is changing the number of transistor pairs or ?fingers? that drive the i/o pad. figure 15 shows a simplified output stage. the behavior of the pad is affected by the configuration register, the output port data, and the current control register. when the current control register bits are programmed to 10b, then only two of the fingers are active, reducing the current drive capability by 50 %. fig 13. high value resistor in parallel with the led fig 14. device supplied by a lower voltage 002aag164 led v dd pn 100 k v dd 002aag165 led v dd pn 3.3 v 5 v fig 15. simplified output stage v dd p0 to p7 configuration register 002aah108 decoder pmos_en0 pmos_en1 pmos_en2 pmos_en3 nmos_en3 nmos_en2 nmos_en1 nmos_en0 output port register current control register pmos_en[3:0] nmos_en[3:0]
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 17 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port reducing the current drive capa bility may be desirable to redu ce system noise. when the output switches (transitions from h/l), there is a peak curr ent that is a function of the output drive selection. this peak current runs through v dd and v ss package inductance and will create noise (some radi ated, but more critically simultaneous switching noise (ssn)). in other words, switching many outpu ts at the same time will create ground and supply noise. the output drive strength co ntrol through the current control registers allows the user to mitigate ssn issues without the need of additional external components. 8.3 12 v tolerant i/os the pcal9554b/pcal9554c device scr group reference diode can go up to 10 v before latch back to 8 v. the esd gate oxide will prot ect the device, but not if used continually. therefore, to achieve 12 v toler ant i/os, the external protection circuitry (diode) must be used as shown in figure 16 . fig 16. external protection circuitry pcal9554b pcal9554c a0 v dd a1 sda a2 scl p0 int p1 p7 p2 p6 p3 p5 v ss p4 002aah210 +5 v +12 v
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 18 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 8.4 power-on reset requirements in the event of a glitch or data corruption, pcal9554b/pcal9554c can be reset to its default conditions by using the power-on rese t feature. power-on reset requires that the device go through a power cycle to be complete ly reset. this reset also happens when the device is powered on for the first time in an application. the two types of power-on reset are shown in figure 17 and figure 18 . ta b l e 1 8 specifies the performance of the power-on reset feature for pcal9554b/pcal9554c for both types of power-on reset. fig 17. v dd is lowered below 0.2 v or 0 v and then ramped up to v dd fig 18. v dd is lowered below the por threshold, then ramped back up to v dd 002aah329 v dd time ramp-up ramp-down (dv/dt) r (dv/dt) f re-ramp-up (dv/dt) r time to re-ramp when v dd drops below 0.2 v or to v ss t d(rst) 002aah330 v dd time ramp-down (dv/dt) f ramp-up (dv/dt) r time to re-ramp when v dd drops to v por(min) ? 50 mv t d(rst) v i drops below por levels
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 19 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port [1] level that v dd can glitch down to with a ramp rate of 0.4 ? s/v, but not cause a functional disruption when t w(gl)vdd <1 ? s. [2] glitch width that will not cause a functional disruption when ? v dd(gl) =0.5 ? v dd . glitches in the power supply can also affect the power-on reset performance of this device. the glitch width (t w(gl)vdd ) and glitch height ( ? v dd(gl) ) are dependent on each other. the bypass capacitance, source impedan ce, and device impedance are factors that affect power-on reset performance. figure 19 and ta b l e 1 8 provide more information on how to measure thes e specifications. v por is critical to the power-on reset. v por is the voltage level at which the reset condition is released and all the registers and the i 2 c-bus/smbus state machine are initialized to their default states. the value of v por differs based on the v dd being lowered to or from 0v. figure 20 and ta b l e 1 8 provide more details on this specification. table 18. recommended supply sequencing and ramp rates t amb =25 ? c (unless otherwise noted). not tested; specified by design. symbol parameter condition min typ max unit (dv/dt) f fall rate of change of voltage figure 17 0.1 - 2000 ms (dv/dt) r rise rate of change of voltage figure 17 0.1 - 2000 ms t d(rst) reset delay time figure 17 ; re-ramp time when v dd drops to v ss 1- - ? s figure 18 ; re-ramp time when v dd drops to v por(min) ? 50 mv 1- - ? s ? v dd(gl) glitch supply voltage difference figure 19 [1] --1.0v t w(gl)vdd supply voltage glitch pulse width figure 19 [2] --10 ? s v por(trip) power-on reset trip voltage falling v dd 0.7--v rising v dd --1.4v fig 19. glitch width and glitch height fig 20. power-on reset voltage (v por ) 002aah331 v dd time t w(gl)vdd ?v dd(gl) 002aah332 por time v dd time v por (rising v dd ) v por (falling v dd )
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 20 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 8.5 device current consumption with internal pull-up and pull-down resistors the pcal9554b; pcal9554c integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. since these pull-up and pull-down resistors are internal to the device itself, they contribute to the current consumption of the device and must be considered in the overall system design. the pull-up or pull-down function is selected in register 44h, while the resistor is connected by the enable register 43h. the configuration of the resistors is shown in figure 6 . if the resistor is configured as a pull-up, that is, connected to v dd , a current will flow from the v dd pin through the resistor to ground when the pin is held low. this current will appear as additional i dd upsetting any current consumption measurements. in the same manner, if the resistor is config ured as a pull-down and the pin is held high, current will flow from the power su pply through the pin to the v ss pin. while this current will not be measured as part of i dd , one must be mindful of the 200 ma limiting value through v ss . the pull-up and pull-down resistors are simple resistors and the current is linear with voltage. the resistance specification for these devices spans from 50 k ? with a nominal 100 k ? value. any current flow through these resi stors is additive by the number of pins held high or low and the current can be calculated by ohm?s law. see figure 24 for a graph of supply current versus the number of pull-up resistors.
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 21 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 9. limiting values [1] the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 10. recommended operating conditions 11. thermal characteristics [1] the package thermal impedance is calc ulated in accordance with jesd 51-7. table 19. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v v i input voltage [1] ? 0.5 +6.5 v v o output voltage [1] ? 0.5 +6.5 v i ik input clamping current a0, a1, a2, scl; v i <0v - ? 20 ma i ok output clamping current int ; v o <0v - ? 20 ma i iok input/output clamping current p port; v o <0v or v o >v dd - ? 20 ma sda; v o <0v or v o >v dd - ? 20 ma i ol low-level output current continuous; i/o port - 50 ma continuous; sda, int -25ma i oh high-level output current continuous; p port - 25 ma i dd supply current - 160 ma i ss ground supply current - 200 ma p tot total power dissipation - 200 mw t stg storage temperature ? 65 +150 ?c t j(max) maximum junction temperature - 125 ?c table 20. operating conditions symbol parameter conditions min max unit v dd supply voltage 1.65 5.5 v v ih high-level input voltage scl, sda 0.7 ? v dd 5.5 v a0, a1, a2, p port 0.7 ? v dd 5.5 v v il low-level input voltage scl, sda ? 0.5 0.3 ? v dd v a0, a1, a2, p port ? 0.5 0.3 ? v dd v i oh high-level output current p port - 10 ma i ol low-level output current p port - 25 ma t amb ambient temperature operating in free air ? 40 +85 ?c table 21. thermal characteristics symbol parameter conditions max unit z th(j-a) transient thermal impedance from junction to ambient hvqfn16 package [1] 53 k/w TSSOP16 package [1] 108 k/w
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 22 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 12. static characteristics table 22. static characteristics t amb = ? 40 ? c to +85 ? c; v dd = 1.65 v to 5.5 v; unless otherwise specified. symbol parameter conditions min typ [1] max unit v ik input clamping voltage i i = ? 18 ma ? 1.2--v v por power-on reset voltage v i =v dd or v ss ; i o =0ma - 1.1 1.4 v v oh high-level output voltage [2] pport; i oh = ? 8 ma; ccx = 11b v dd =1.65v 1.2--v v dd = 2.3 v 1.8 - - v v dd =3v 2.6--v v dd = 4.5 v 4.1 - - v pport; i oh = ? 2.5 ma and ccx = 00b; i oh = ? 5 ma and ccx = 01b; i oh = ? 7.5 ma and ccx = 10b; i oh = ? 10 ma and ccx = 11b v dd =1.65v 1.1--v v dd = 2.3 v 1.7 - - v v dd =3v 2.5--v v dd = 4.5 v 4.0 - - v v ol low-level output voltage [2] pport; i ol =8ma; ccx=11b v dd =1.65v --0.45v v dd =2.3v --0.25v v dd =3v --0.25v v dd =4.5v --0.2v pport; i ol = 2.5 ma and ccx = 00b; i ol = 5 ma and ccx = 01b; i ol = 7.5 ma and ccx = 10b; i ol = 10 ma and ccx = 11b v dd =1.65v --0.5v v dd =2.3v --0.3v v dd =3v --0.25v v dd =4.5v --0.2v i ol low-level output current v ol = 0.4 v; v dd = 1.65 v to 5.5 v sda 3--ma int 315 [3] -ma i i input current v dd =1.65v to 5.5v scl, sda; v i =v dd or v ss --0.1 ? a a0, a1, a2; v i =v dd or v ss --? 1 ? a i ih high-level input current p port; v i =v dd ; v dd =1.65v to 5.5v - - 1 ? a i il low-level input current p port; v i =v ss ; v dd = 1.65 v to 5.5 v - - 1 ? a
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 23 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port [1] for i dd , all typical values are at nominal supply voltage (1.8 v, 2.5 v, 3.3 v, 3.6 v or 5 v v dd ) and t amb =25 ? c. except for i dd , the typical values are at v dd = 3.3 v and t amb =25 ? c. [2] the total current sourced by all i/os must be limited to 160 ma , and total current sunk by all i/os must be limited to 200 ma. [3] typical value for t amb =25 ? c. v ol = 0.4 v and v dd = 3.3 v. typical value for v dd <2.5v, v ol =0.6v. i dd supply current sda, p port, a0, a1, a2; v i on scl, sda = v dd or v ss ; v i on p port and a0, a1, a2 = v dd ; i o =0ma;i/o=inputs; f scl = 400 khz v dd = 3.6 v to 5.5 v - 10 25 ? a v dd = 2.3 v to 3.6 v - 6.5 15 ? a v dd = 1.65 v to 2.3 v - 4 9 ? a scl, sda, p port, a0, a1, a2; v i on scl, sda = v dd or v ss ; v i on p port and a0, a1, a2 = v dd ; i o =0ma;i/o=inputs; f scl = 0 khz v dd = 3.6 v to 5.5 v - 1.5 7 ? a v dd = 2.3 v to 3.6 v - 1 3.2 ? a v dd = 1.65 v to 2.3 v - 0.5 1.7 ? a active mode; p port, a0, a1, a2; v i on p port and a0, a1, a2 = v dd ; i o =0ma;i/o=inputs; f scl = 400 khz, continuous register read v dd = 3.6 v to 5.5 v - 60 125 ? a v dd = 2.3 v to 3.6 v - 40 75 ? a v dd = 1.65 v to 2.3 v - 20 45 ? a with pull-ups enabled; p port, a0, a1, a2; v i on scl, sda = v dd or v ss ; v i on p port = v ss ; v i on a0, a1, a2 = v dd or v ss ; i o = 0 ma; i/o = inputs with pull-up enabled; f scl =0khz v dd = 1.65 v to 5.5 v - 0.55 0.75 ma ? i dd additional quiescent supply current scl, sda; one input at v dd ? 0.6 v, other inputs at v dd or v ss ; v dd = 1.65 v to 5.5 v --25 ? a p port, a0, a1; one input at v dd ? 0.6 v, other inputs at v dd or v ss ; v dd =1.65vto5.5v --80 ? a c i input capacitance v i =v dd or v ss ; v dd =1.65vto5.5v - 6 7 pf c io input/output capacitance sda, scl; v i/o =v dd or v ss ;v dd =1.65vto5.5v - 78pf pport; v i/o =v dd or v ss ;v dd =1.65vto5.5v -7.58.5pf r pu(int) internal pull-up resistance input/output 50 100 150 k ? r pd(int) internal pull-down resistance input/output 50 100 150 k ? table 22. static characteristics ?continued t amb = ? 40 ? c to +85 ? c; v dd = 1.65 v to 5.5 v; unless otherwise specified. symbol parameter conditions min typ [1] max unit
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 24 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 12.1 typical characteristics fig 21. supply current versus ambient temperature fig 22. standby supply current versus ambient temperature t amb =25 ? c fig 23. supply current versus supply voltage fig 24. supply current versus number of i/o held low 8 12 4 16 20 i dd (a) 0 t amb (c) ?40 85 60 10 35 ?15 002aah333 v dd = 5.5 v 5.0 v 3.6 v 3.3 v 2.5 v 2.3 v v dd = 1.8 v 1.65 v 600 800 400 1400 i dd(stb) (na) 0 t amb (c) ?40 85 60 10 35 ?15 002aah334 v dd = 5.5 v 5.0 v 3.6 v 3.3 v 200 1000 2.5 v 2.3 v 1.8 v 1.65 v 8 12 4 16 20 i dd (a) 0 v dd (v) 1.5 5.5 4.5 2.5 3.5 002aah335 0 0.6 0.4 0.2 0.8 i dd (ma) number of i/o held low 08 6 24 002aah212 t amb = ?40 c 25 c 85 c
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 25 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port a. v dd =1.65v b. v dd =1.8v c. v dd =2.5v d. v dd =3.3v e. v dd =5.0v f. v dd =5.5v fig 25. i/o sink current versus low-le vel output voltage with ccx.x = 11b v ol (v) 0 0.3 0.2 0.1 002aaf578 15 25 35 i sink (ma) 0 t amb = ?40 c 25 c 85 c 5 10 20 30 v ol (v) 0 0.3 0.2 0.1 002aaf579 15 25 35 i sink (ma) 0 t amb = ?40 c 25 c 85 c 5 10 20 30 v ol (v) 0 0.3 0.2 0.1 002aaf580 20 50 i sink (ma) 0 t amb = ?40 c 25 c 85 c 10 30 40 v ol (v) 0 0.3 0.2 0.1 002aaf581 20 40 60 i sink (ma) 0 t amb = ?40 c 25 c 85 c v ol (v) 0 0.3 0.2 0.1 002aaf582 30 50 70 i sink (ma) 0 t amb = ?40 c 25 c 85 c 10 20 40 60 v ol (v) 0 0.3 0.2 0.1 002aaf583 30 50 70 i sink (ma) 0 t amb = ?40 c 25 c 85 c 10 20 40 60
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 26 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port a. v dd =1.65v b. v dd =1.8v c. v dd =2.5v d. v dd =3.3v e. v dd =5.0v f. v dd =5.5v fig 26. i/o source current versus high-level output voltage with ccx.x = 11b v dd ? v oh (v) 0 0.6 0.4 0.2 002aah110 10 20 30 i source (ma) 0 t amb = ?40 c 25 c 85 c v dd ? v oh (v) 0 0.6 0.4 0.2 002aah111 15 25 35 i source (ma) 0 t amb = ?40 c 25 c 85 c 5 10 20 30 v dd ? v oh (v) 0 0.6 0.4 0.2 002aah112 20 40 60 i source (ma) 0 t amb = ?40 c 25 c 85 c v dd ? v oh (v) 0 0.6 0.4 0.2 002aah113 30 50 70 i source (ma) 0 t amb = ?40 c 25 c 85 c 10 20 40 60 v dd ? v oh (v) 0 0.6 0.4 0.2 002aah114 30 60 90 i source (ma) 0 t amb = ?40 c 25 c 85 c v dd ? v oh (v) 0 0.6 0.4 0.2 002aah115 30 60 90 i source (ma) 0 t amb = ?40 c 25 c 85 c
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 27 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port (1) v dd = 1.8 v; i sink =10ma (2) v dd = 5 v; i sink =10ma (3) v dd = 1.8 v; i sink =1ma (4) v dd = 5 v; i sink =1ma i source = ? 10 ma fig 27. low-level output voltage versus temperature fig 28. i/o high voltage versus temperature 60 80 20 100 120 v ol (mv) 0 t amb (c) ?40 85 60 10 35 ?15 002aah056 (1) (3) (4) (2) 40 t amb (c) ?40 85 60 10 35 ?15 002aah343 160 120 200 0 v dd ? v oh (mv) v dd = 1.8 v 5 v 80 40
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 28 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 13. dynamic characteristics table 23. i 2 c-bus interface timing requirements over recommended operating free air temperat ure range, unless otherwise specified. see figure 29 . symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max f scl scl clock frequency 0 100 0 400 khz t high high period of the scl clock 4 - 0.6 - ? s t low low period of the scl clock 4.7 - 1.3 - ? s t sp pulse width of spikes that must be suppressed by the input filter 050 0 50ns t su;dat data set-up time 250 - 100 - ns t hd;dat data hold time 0 - 0 - ns t r rise time of both sda and scl signals - 1000 20 300 ns t f fall time of both sda and scl signals - 300 20 ? (v dd /5.5v) 300 ns t buf bus free time between a stop and start condition 4.7 - 1.3 - ? s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - ? s t hd;sta hold time (repeated) start condition 4 - 0.6 - ? s t su;sto set-up time for stop condition 4 - 0.6 - ? s t vd;dat data valid time scl low to sda output valid -3.45 - 0.9 ? s t vd;ack data valid acknowledge time ack signal from scl low to sda (out) low -3.45 - 0.9 ? s table 24. switching characteristics over recommended operating free air temperature range; c l ? 100 pf; unless other wise specified. see figure 29 . symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t v(int) valid time on pin int from p port to int -1-1 ? s t rst(int) reset time on pin int from scl to int -1-1 ? s t v(q) data output valid time from scl to p port - 400 - 400 ns t su(d) data input set-up time from p port to scl 0 - 0 - ns t h(d) data input hold time from p port to scl 300 - 300 - ns
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 29 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 14. parameter measure ment information a. sda load configuration b. transaction format c. voltage waveforms c l includes probe and jig capacitance. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. all parameters and waveforms ar e not applicable to all devices. byte 1 = i 2 c-bus address; byte 2, byte 3 = p port data. (1) see figure 9 . fig 29. i 2 c-bus interface load circuit and voltage waveforms 002aag803 dut c l = 50 pf r l = 1 k sda v dd stop condition (p) data bit 0 (lsb) data bit 7 (msb) ack (a) r/w bit 0 (lsb) address bit 1 address bit 7 (msb) start condition (s) stop condition (p) two bytes for read input port register (1) 002aag952 t low t high t r t f 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd t sp t buf t f t hd;sta t r scl sda t su;dat t hd;dat t f(o) t vd;ack t vd;dat t vd;ack t su;sta t su;sto 002aag804 repeat start condition stop condition
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 30 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port a. interrupt load configuration b. voltage waveforms c l includes probe and jig capacitance. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. all parameters and waveforms ar e not applicable to all devices. (1) pcal9554b address shown. address for pcal9554c is 0111,a2,a1,a0. fig 30. interrupt load circuit and voltage waveforms 002aah069 dut c l = 100 pf r l = 4.7 k int v dd 1 0 0 a2 a1 a0 1 a s0 slave address (1) start condition r/w acknowledge from slave 002aah130 8 bits (one data byte) from port a acknowledge from slave sda 1 no acknowledge from master data into port data from port data 1 data 2 int data 2 data 1 p stop condition t v(int) t rst(int) t su(d) 12345678 scl 9 address t rst(int) a a view a - a int pn t v(int) 0.5 v dd 0.5 v dd view b - b scl 0.5 v dd int r/w a t rst(int) 0.3 v dd 0.7 v dd b b
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 31 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port a. p port load configuration b. write mode (r/w =0) c. read mode (r/w =1) c l includes probe and jig capacitance. t v(q) is measured from 0.7 ? v dd on scl to 50 % i/o (pn) output. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. the outputs are measured one at a time, with one transition per measurement. all parameters and waveforms ar e not applicable to all devices. fig 31. p port load circuit and voltage waveforms 002aag805 dut c l = 50 pf 500 pn 2 v dd 500 002aag806 scl sda p0 a t v(q) 0.3 v dd 0.7 v dd p7 last stable bit unstable data pn 002aag807 scl pn p0 a t h(d) 0.3 v dd 0.7 v dd p7 t su(d)
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 32 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 15. package outline fig 32. package outline sot403-1 (TSSOP16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 33 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port fig 33. package outline sot758-1 (hvqfn16) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.75 1.45 y 1 3.1 2.9 1.75 1.45 e 1 1.5 e 2 1.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot758-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot758-1 hvqfn16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 58 16 13 12 9 4 1 x d e c b a e 2 02-03-25 02-10-21 terminal 1 index area 1/2 e 1/2 e ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 34 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 16. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are:
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 35 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 17.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 34 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 5 and 26 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 34 . table 25. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 26. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 36 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 34. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 37 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 18. soldering: pcb footprints fig 35. pcb footprint for sot403-1 (TSSOP16); reflow soldering dimensions in mm ay by d1 d2 gy hy p1 c gx sot403-1_fr hx sot403-1 solder land occupied area footprint information for reflow soldering of TSSOP16 package ay by gy c hy hx gx p1 generic footprint pattern refer to the package outline drawing for actual layout p2 (0.125) (0.125) d1 d2 (4x) p2 7.200 4.500 1.350 0.400 0.600 5.600 5.300 7.450 5.800 0.650 0.750
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 38 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port fig 36. pcb footprint for sot758-1 (hvqfn16); reflow soldering sot758-1 footprint information for reflow soldering of hvqfn16 package dimensions in mm ax ay bx by d slx sly spx spy gx gy hx hy 4.00 4.00 2.20 2.20 p 0.50 0.24 c 0.90 1.50 1.50 0.30 spy tot 0.90 spx tot 0.90 0.30 3.30 3.30 4.25 4.25 nspx nspy 22 sot758-1_fr occupied area solder land plus solder paste solder land solder paste deposit issue date 12-03-07 12-03-08 aybysly ax bx slx gx hx d gy hy (0.105) spx c p 0.025 0.025 spy spx tot spy tot nspx nspy
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 39 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 19. abbreviations 20. revision history table 27. abbreviations acronym description acpi advanced configuration and power interface cbt cross-bar technology cdm charged-device model cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge fet field-effect transistor ff flip-flop gpio general purpose input/output hbm human body model i 2 c-bus inter-integrated circuit bus i/o input/output led light emitting diode lp low-pass lsb least significant bit msb most significant bit por power-on reset scr silicon controlled rectifier smbus system management bus table 28. revision history document id release date data sheet status change notice supersedes pcal9554b_pcal9554c v.2 20121210 product data sheet - pcal9554b_pcal9554c v.1 modifications: ? section 8.5 ? device current consumption with intern al pull-up and pull-down resistors ? , second paragraph: first sentence is correct ed from ?the pull-up or pull-down function is selected in registers 48h and 49h, whil e the resistor is connected by the enable registers 46h and 47h.? to ?the pull-up or pu ll-down function is selected in register 44h, while the resistor is connect ed by the enable register 43h.? ? table 22 ? static characteristics ? : conditions updated for characteristic c io : added ?sda, scl? to first condition row; added ?p port? to second condition row pcal9554b_pcal9554c v.1 20121003 product data sheet - -
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 40 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 21.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 21.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pcal9554b_pcal9554c all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserv ed. product data sheet rev. 2 ? 10 december 2012 41 of 42 nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 21.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 22. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pcal9554b; pcal9554c low-voltage 8-bit i 2 c-bus/smbus low power i/o port ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 10 december 2012 document identifier: pcal9554b_pcal9554c please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 agile i/o features . . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 6.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pointer register and command byte . . . . . . . . . 5 6.3 interface definition . . . . . . . . . . . . . . . . . . . . . . 6 6.4 register descriptions . . . . . . . . . . . . . . . . . . . . 6 6.4.1 input port register (00h) . . . . . . . . . . . . . . . . . . 6 6.4.2 output port register (01h) . . . . . . . . . . . . . . . . . 6 6.4.3 polarity inversion register (02h) . . . . . . . . . . . . 7 6.4.4 configuration register (03h) . . . . . . . . . . . . . . . 7 6.4.5 output drive strength re gisters (40h, 41h) . . . . 7 6.4.6 input latch register (42h). . . . . . . . . . . . . . . . . . 8 6.4.7 pull-up/pull-down enable register (43h) . . . . . . 8 6.4.8 pull-up/pull-dow n selection register (44h). . . . . 9 6.4.9 interrupt mask register (45h ) . . . . . . . . . . . . . . 9 6.4.10 interrupt status register (46h) . . . . . . . . . . . . . . 9 6.4.11 output port configuration register (47h) . . . . . 10 6.5 i/o port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.6 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11 6.7 interrupt output (int ) . . . . . . . . . . . . . . . . . . . 11 7 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 write commands. . . . . . . . . . . . . . . . . . . . . . . 12 7.2 read commands . . . . . . . . . . . . . . . . . . . . . . 13 8 application design-in information . . . . . . . . . 15 8.1 minimizing i dd when the i/os are used to control leds . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 output drive strength control . . . . . . . . . . . . . 16 8.3 12 v tolerant i/os . . . . . . . . . . . . . . . . . . . . . . 17 8.4 power-on reset requirements . . . . . . . . . . . . . 18 8.5 device current cons umption with internal pull-up and pull-down resistors . . . . . . . . . . . . 20 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 21 10 recommended operating conditions. . . . . . . 21 11 thermal characteristics . . . . . . . . . . . . . . . . . 21 12 static characteristics. . . . . . . . . . . . . . . . . . . . 22 12.1 typical characteristics . . . . . . . . . . . . . . . . . . 24 13 dynamic characteristics . . . . . . . . . . . . . . . . . 28 14 parameter measurement in formation . . . . . . 29 15 package outline. . . . . . . . . . . . . . . . . . . . . . . . 32 16 handling information . . . . . . . . . . . . . . . . . . . 34 17 soldering of smd packages . . . . . . . . . . . . . . 34 17.1 introduction to soldering. . . . . . . . . . . . . . . . . 34 17.2 wave and reflow soldering. . . . . . . . . . . . . . . 34 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 34 17.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 35 18 soldering: pcb footprints . . . . . . . . . . . . . . . 37 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39 20 revision history . . . . . . . . . . . . . . . . . . . . . . . 39 21 legal information . . . . . . . . . . . . . . . . . . . . . . 40 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 40 21.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 21.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 40 21.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41 22 contact information . . . . . . . . . . . . . . . . . . . . 41 23 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

▲Up To Search▲

Price & Availability of TSSOP16

	To Download TSSOP16 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .